Shunsuke OKURA Tetsuro OKURA Toru IDO Kenji TANIGUCHI
A reference voltage buffer for a multibit/stage pipelined ADC is described, where a settling boost technique is used to improve the settling response of the pipelined stages. A 12 bit 18 MHz pipelined ADC with the buffer is designed and simulated based on a 0.35 µm CMOS process. According to simulation results, the power consumed by the reference voltage buffer is reduced by 33% compared to that without the settling boost technique.
Boon-Keat TAN Ryuji YOSHIMURA Toshimasa MATSUOKA Kenji TANIGUCHI
This paper describes a new architecture-based microprocessor, a dynamically programmable parallel processor (DPPP), that consists of large numbers of simplified ALUs (sALU) as processing blocks. All sALUs are interconnected via a code division multiple-access bus interface that provides complete routing flexibility by establishing connections virtually through code-matching instead of physical wires. This feature is utilized further to achieve high parallelism and fault tolerance. High fault tolerance is realized without the limitations of conventional fabrication-based techniques nor providing spare elements. Another feature of the DPPP is its simple programmability, as it can be configured by compiling numerical formula input using the provided user auto-program interface. A prototype chip based on the proposed architecture has been implemented on a 4.5 mm 4.5 mm chip using 0.6 µm CMOS process.
Masaharu KIRIHARA Kenji TANIGUCHI
The basic operation characteristics of an asymmetric turnstile which transfers each electron one by one in one direction is described. A novel single electron counter circuit consisting of the asymmetric turnstiles, a load capacitor and an inverter which counts the number of high inputs is proposed. Monte Carlo circuit simulations reveal that the gate clock time of the counter circuit should be long enough to achieve allowable minimum error rate. The counter circuit implementing asymmetric single electron turnstiles is demonstrated to be applicable to a noise reduction system, a Winner-Take-All circuit and an artificial neuron circuit.
Kenji TANIGUCHI Yukihiro HIGASHIWAKI
In the present paper, procedures for extracting nucleoli from leukocyte images are proposed. Main processed procedures consist of the filtering operation in the frequency domain, the edge preserving smoothing, the extraction of the nuclear region, the edge detection and the decision of nucleolar regions. By applying proposed procedures, nucleoli can be extracted easily and precisely from the nucleus if we can clearly see nucleoli with human eyes. We were able to achieve the correct discrimination of 82 percent of nucleoli in immature leukocytes.
Tsukasa IDA Shinsaku SHIMIZU Toshimasa MATSUOKA Kenji TANIGUCHI
Wired CDMA interface with adaptivity for interconnect capacitances is designed to receive transmitted data even under a wide variety of connection topologies. The variable gain amplifier (VGA) is one of key circuit blocks to realize the adaptivity for interconnect capacitances. The system level numerical simulations derive the VGA specifications that the required VGA gain range is from 0.37 to 2.0, which can be realized easily using a multiple-differential-pair technique.
Daisuke KANEMOTO Toru IDO Kenji TANIGUCHI
A low power and high performance with third order delta-sigma modulator for audio applications, fabricated in a 0.18 µm CMOS process, is presented. The modulator utilizes a third order noise shaping with only one opamp by using an opamp sharing technique. The opamp sharing among three integrator stages is achieved through the optimal operation timing, which makes use of the load capacitance differences between the three integrator stages. The designed modulator achieves 101.1 dB signal-to-noise ratio (A-weighted) and 101.5 dB dynamic range (A-weighted) with 7.5 mW power consumption from a 3.3 V supply. The die area is 1.27 mm2. The fabricated delta-sigma modulator achieves the highest figure-of-merit among published high performance low power audio delta-sigma modulators.
Hyunju HAM Toshimasa MATSUOKA Kenji TANIGUCHI
A signal detection system using noise statistical processing is proposed. By approaching the problems of low voltage and high noise from miniaturization of a device from a stochastic point of view, a faint-signal receiving system that can effectively detect subthreshold and noise level signals has been developed. In addition, an alternative to statistical processing is proposed, and would be successfully implemented on a circuit. For the proposed signal detection method, the detection sensitivity was investigated using numerical simulation, and the detection sensitivity was sufficiently high to detect even a signal with a signal-to-inherent-noise ratio of -14 dB. Thus, it is anticipated that the application of this system to an integrated circuit will have a significant impact on signal processing.
Toshimasa MATSUOKA Jun WANG Takao KIHARA Hyunju HAM Kenji TANIGUCHI
This paper introduces several techniques for achieving RF and analog CMOS circuits for wireless communication systems under ultra-low-voltage supply, such as 0.5 V. Forward body biasing and inverter-based circuit techniques were applied in the design of a feedforward Δ-ΣA/D modulator operating with a 0.5 V supply. Transformer utilization is also presented as an inductor area reduction technique. In addition, application of stochastic resonance to A/D conversion is discussed as a future technology.
Hisayasu SATO Takaya MARUYAMA Toshimasa MATSUOKA Kenji TANIGUCHI
This paper presents the design consideration of a four-stage variable gain amplifier (VGA) with a wide dynamic range for receivers. The VGA uses parallel amplifiers for the first and second amplifiers in order to improve the input third-order intercept point (IIP3) in the low gain region. To investigate the behavior of the VGA, the gain and linearity analyses are newly derived for the parallel amplifiers, and are compared with the measured results. In addition, the principle of the temperature compensation is described. The gain control range of 110 dB, the IP1 dB of -11 dBm, and noise figure (NF) of 5.1 dB were measured using a 0.5 µm 26 GHz fT BiCMOS process.
Shunsuke OKURA Tetsuro OKURA Bogoda A. INDIKA U.K. Kenji TANIGUCHI
This paper describes the design of a random access memory (RAM) bank with a 0.35-µm CMOS process for column-parallel analog/digital converters (ADC) utilized in CMOS imagers. A dynamic latch is utilized that expends neither input DC nor drain current during the monitoring phase. Accuracy analysis of analog/digital conversion error in the RAM bank is discussed to ensure low power consumption of a counter buffer circuit. Moreover, the counter buffer utilizes a combination of NMOS and CMOS buffers to reduce power consumption. Total power consumption of a 10-bit 800-column 40 MHz RAM bank is 2.9 mA for use in an imager.
Mitsuo NAKAMURA Hideki SHIMA Toshimasa MATSUOKA Kenji TANIGUCHI
For wireless communication, a low-voltage monolithic LC-tank CMOS voltage-controlled-oscillator (VCO) is developed with 0.2-µm fully-depleted silicon-on-insulator (SOI) CMOS process technology. The VCO features a double-tuning technique to achieve a wide tuning range with lateral p-n junction varactors. The VCO has the following features at the supply voltage of 1.5 V: (1) Output frequency range from 1.07 GHz to 1.36 GHz, (2) Third-harmonic below -37 dBc, and (3) Phase noise of -120 dBc/Hz at 1 MHz offset frequency.
Yoshiyuki SHIMIZU Toshimasa MATSUOKA Kenji TANIGUCHI
The threshold voltage mismatch of FD (Fully depleted) SOI (Silicon on insulator) devices have been studied. Floating body MOSFETs operating at high drain voltage show a large mismatch in the threshold voltage compared with body-tied MOSFETs. Those experimental data under different drain voltages indicate that both floating body effect and DIBL (Drain induced barrier lowering) are involved in the threshold voltage mismatch of floating body MOSFETs.
Takao KIHARA Guechol KIM Masaru GOTO Keiji NAKAMURA Yoshiyuki SHIMIZU Toshimasa MATSUOKA Kenji TANIGUCHI
We propose a design methodology of a low-voltage CMOS low-noise amplifier (LNA) consisting of a common-source and a common-gate stages. We first derive equations of power gain, noise figure (NF) and input third-order intercept point (IIP3) of the two-stage LNA. A design methodology of the LNA is presented by using graphs based on analytical equations. A 1-V 5.4-GHz LNA was implemented in 0.15-µm fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. Measurement results show a power gain of 23 dB, NF of 1.7 dB and IIP3 of -6.1 dBm with a power consumption of 8.3 mW. These measured results are consistent with calculated results, which ensures the validity of the derived equations and the proposed design methodology.
Takao KIHARA Toshimasa MATSUOKA Kenji TANIGUCHI
Previously reported wideband CMOS low-noise amplifiers (LNAs) have difficulty in achieving both wideband input impedance matching and low noise performance at low power consumption and low supply voltage. We present a transformer noise-canceling wideband CMOS LNA based on a common-gate topology. The transformer, composed of the input and shunt-peaking inductors, partly cancels the noise originating from the common-gate transistor and load resistor. The combination of the transformer with an output series inductor provides wideband input impedance matching. The LNA designed for ultra-wideband (UWB) applications is implemented in a 90 nm digital CMOS process. It occupies 0.12 mm2 and achieves |S11|<-10 dB, NF<4.4 dB, and |S21|>9.3 dB across 3.1-10.6 GHz with a power consumption of 2.5 mW from a 1.0 V supply. These results show that the proposed topology is the most suitable for low-power and low-voltage UWB CMOS LNAs.
Shinsaku SHIMIZU Toshimasa MATSUOKA Kenji TANIGUCHI
An efficient data transmission interface for VLSI systems, Multi-Bit Parallel Code Division Multiple Access (MB/P-CDMA) interface, has been designed with 0.35 µm CMOS technology. The proposed interface achieves 1.12 Gb/s data rate (80 MHz, 8 bit bus) using multi-bit transmission at each clock per transmitter. The proposed CDMA interface ensures higher speed operation than conventional interface even in noisy environments. Each of the transmitters and receivers occupies the die area of 290 360 µm2 and 240 280 µm2, respectively.
Hiroyasu YOSHIZAWA Kenji TANIGUCHI Hiroyuki SHIRAHAMA Kenichi NAKASHI
To realize the high speed and low power CMOS Phase Locked Loop, we have developed new components of PLL: VCO and PFD. In the VCO, high speed and low power is realized with source coupled inverter pairs in the single loop three gate ring oscillator. And in the PFD, low power and small chip area are realized with the dynamic inverter. And with the simple design adjustment, both reduction of dead zone and immunity of current fluctuation at "O" output are implemented in Charge Pump. A fully CMOS PLL with these components have been designed with 0.8µ CMOS. At 622MHz operation, the power dissipation of 18mW is achieved by SPICE simulation.
Indika U. K. BOGODA APPUHAMYLAGE Shunsuke OKURA Toru IDO Kenji TANIGUCHI
This paper proposes an area efficient, low power, fractional CMOS bandgap reference (BGR) utilizing switched-current and current-memory techniques. The proposed circuit uses only one parasitic bipolar transistor and built-in current source to generate reference voltage. Therefore significant area and power reduction is achieved, and bipolar transistor device mismatch is eliminated. In addition, output reference voltage can be set to almost any value. The proposed circuit is designed and simulated in 0.18 µm CMOS process, and simulation results are presented. With a 1.6 V supply, the reference produces an output of about 628.5 mV, and simulated results show that the temperature coefficient of output is less than 13.8 ppm/ in the temperature range from 0 to 100. The average current consumption is about 8.5 µA in the above temperature range. The core circuit, including current source, opamp, current mirrors and switched capacitor filters, occupies less than 0.0064 mm2 (80 µm×80 µm).
Guechol KIM Yoshiyuki SHIMIZU Bunsei MURAKAMI Masaru GOTO Keisuke UEDA Takao KIHARA Toshimasa MATSUOKA Kenji TANIGUCHI
A new small-signal model for fully depleted silicon-on-insulator (FD-SOI) MOSFETs operating at RF frequencies is presented. The model accounts for the non-quasi-static effect by determining model parameters using a curve fitting procedure to reproduce the frequency response of FD-SOI MOSFETs. The accuracy of the model is validated by comparison of S parameters with measured results in the range from 0.2 GHz to 20 GHz.
Yu TAMURA Toru IDO Kenji TANIGUCHI
This paper presents a technique to enhance in-band mismatch noise reduction of multi-stage second order Dynamic Element Matching (DEM) in multi-level ΔΣ Digital-to-Analog Converters (DACs). The presented technique changes an operational behavior of multi-stage DEM to reduce mismatch noise at in-band frequency. This change improves mismatch noise shaping performance for small amplitude input signals. Simulation result using 2-stage second order DEM and a third order 17-level ΔΣ modulator with 0.5% analog element mismatch shows 3.4 dB dynamic range improvement.